[Beowulf] Re: GPU boards and cluster servers.

Maurice Hilarius maurice at harddata.com
Fri Sep 5 07:32:50 PDT 2008


Kozin, I (Igor) wrote:
> ..
> Yes, memory bandwidth can be a problem for Intel servers. Now. But we
> all know this is going to change soon.
>   
"Soon" ? We are hearing about a year.
In the meantime AMD "Shanghai" with 4 cores on 45nm process ships this year.
Also 6MB of L3 cache.

This bump basically puts the AMD line even with the Intel on clock
speeds with Intel.
Meaning Intel will have to drop the prices on the higher clocks to be
competitive, a good thing for all of us.

Come mid 2009 AMD releases "Istanbul" with 6 cores, 6MB L3 cache.
HT3 means the memory bandwidth interconnects double in speed,
pulling them well ahead of the new Intel designs in terms of memory
bandwidth.
And, remember these still use simple DDR2. No FBDIMMS, DDR3, or other
expensive tricks.

If we are forward looking, expect 8 and 12 core Opterons by the end of 2009.

Fiorano chipset comes then too, with 4 x PCI-E @ 2.0

> More surprisingly Opteron based servers do not offer PCIe Gen2 just yet.
>   
No, but not really needed (yet)
Barcelona already offers 2 links to the CPUs at 8GB/sec, so supporting
enough PCI-E lanes for any board designs is easy.
When you can support 4 x PCI-E 16 lanes RIGHT NOW ( as opposed to 4 x
PCI-E 8 lanes on Intel chipsets),
Why do you need PCI-E 2.0?
Especially when you have the memory bandwidth to support it.

Until Intel chipsets get better bandwidth to RAM all the slots in the
world are irrelevant.


> Perhaps it was long time ago when I checked it last time. The paper
> cited above indicates very significant impact of PCIe Gen2 on the
> bandwidth.
>
>   
They do, on the newer chipsets.


-- 
With our best regards,

//Maurice W. Hilarius         Telephone: 01-780-456-9771/
/Hard Data Ltd.                FAX:          01-780-456-9772/
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