[Beowulf] Shanghai vs Barcelona, Shanghai vs Nehalem
bill at cse.ucdavis.edu
Wed Oct 22 14:00:48 PDT 2008
> AMD could MCM 2 shanghai chips, resulting in 6 cores (2 tri-cores) or 8
AMD socket supports 3 hypertransport channels and 2 64 bit memory busses.
Somehow you would have to connect these to 2 piece of silicon. I've not heard
that AMD has much MCM experience (unlike ibm and intel).
Intel on the other hand had a very easy time. Intel's dual die setup was
trivial in comparison, each die was designed to sit on a shared bus and the
memory controller is offchip.
Seems like AMD would have put in a 3rd chip into the MCM, or some how disable
some functionality on one die and share the memory bus/HT from the other chip.
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