[Beowulf] precise synchronization of system clocks

Robert G. Brown rgb at phy.duke.edu
Wed Oct 1 21:14:06 PDT 2008

On Wed, 1 Oct 2008, NiftyOMPI Mitch wrote:

> The dI/dT  for processors can be quite high.
> AMD Phenomâ„¢ X4 Quad-Core is listed as a 140 watt part (thermal)
> it is unlikely that all 450 million transistors are active in an idle
> loop.  Tom's Hardware list the idle power at 21 watts.  The speed at
> which a modern processor can go from idle to full power is astonishing.
> The local on board power supply regulation must respond very quickly. The
> delta
> from 21 to 140 fit inside one half cycle of a 50/60 Hz AC mains service.  So
> inside
> of one AC cycle the part can move from 21 to 140.... which is large when
> multiplied by a 1000 node dual socket cluster.  I do know of clusters and
> labs of workstations that power on hosts and disks in sequence to limit the
> startup power surge.    Lots of us have been at it long enough to know  that
> induction motors like elevators, refrigeration compressors and even vacuums
> can hit the mains
> hard enough to trigger errors.  My home vacuum does dim the lights a little
> bit.

I understand inductive surge when powering up, I understand in detail
browning out a primary power transformer, but I think those are
different issues and irrelevant here.

So far, using my trusty Kill-a-Watt on real world nodes, I haven't seen
more than a 30% differential draw loaded to unloaded.  Large parts of
the CPU require power at all times to function.  Memory, for example,
both on and offboard.  Nearly everything inside a computer has a
nontrivial idle draw, plus (sure) peak draw when it or one of its
subsystems are in use.

Exceptions are modern laptops -- with variable speed clocks, they draw
much less idling than they do at speed, in part because power (idle or
otherwise) IS very nearly proportional to CPU clock in at least parts of
the system.  And I don't really know how the latest designs do in this
regard -- but there is a tendency to design the bleeding edge
PERFORMANCE CPUs to work at "constant heat", as a major rate limiting
factor in CPU design is getting rid of heat from the package.  It's one
reason they don't just crank the clock to infinity and beyond -- not the
only one, but a major one.

Multicores, of course, may function like hybrid cars, and somehow run
more nearly idle when they are idle.  But I'd have to hear from someone
who slapped a KaW on an actual system and clocked it from idle (solidly
post-boot, running the OS, at idle "equilibrium") to loaded (running
flat out on e.g. a benchmark suite that loads all cores and/or the
memory etc.).  Has anyone actually done this and observed (say) a 2 or 3
to 1 increase in power draw loaded to idle?  50W idle to 200W loaded in
1 second?  150W idle to 200W loaded is more like what I've seen...

> In normal  practice I doubt that this is an issue but synchronization in the
> extreme is interesting in its details and side effects.

I completely agree with this, both parts.  Although if one IS bumping
from 50->200W "instantly" on not even an entire cluster but just all the
nodes on a single circuit, that's popping over a KW on a 20A line --
ballpark where one MIGHT see something inductive (although as I said,
probably nothing that the power supply capacitor(s) cannot buffer,
although I'm too tired to compute the number of joules (watt-seconds)
one can probably deliver and what RC probably is, etc).  Popping
multiple (as in 10+) KW in less than a 60 Hz cycle would very likely be
hard on the primary, no doubt about it.


        T o m   M i t c h e l l

Robert G. Brown                            Phone(cell): 1-919-280-8443
Duke University Physics Dept, Box 90305
Durham, N.C. 27708-0305
Web: http://www.phy.duke.edu/~rgb
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