[Beowulf] Tilera to Introduce 64-Core Processor

Peter St. John peter.st.john at gmail.com
Thu Oct 18 11:21:16 PDT 2007


Richard,

I found
http://www.cis.upenn.edu/~milom/cis501-Fall05/lectures/10_dlp.pdf
which I think will clarify this taxonomy for me, and it ties in to the
Single/many instruction S/M data thing too. Gosh this "beowulfry" thing has
alot of stuff. Arithmetic Algebraic Geometry is simpler.

Peter (lying about AAG)


On 10/18/07, richard.walsh at comcast.net <richard.walsh at comcast.net> wrote:
>
>
>
> -------------- Original message --------------
> From: "Peter St. John" <peter.st.john at gmail.com>
> DLP? Wiki has entries for Indtruction Level Parallelism and Thread LP
> (alsom Memory LP) but
> not DLP?
>
> Hey Peter,
>
> That would be "data level parallelism".  So, ILP is very low level
> parallelism which
>
>
,,,
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