[Beowulf] Teraflop chip hints at the future

[Alan Louis Scheinine]

Richard Walsh wrote:
  > why not just use an FPGA ...  ;-)

    I taught myself VHDL and programmed two algorithms
in Mitrion-C, but I decided that less general hardware
such as CBE (Cell) is better for HPC.  I made an estimate
of how much area on a FPGA is needed for a group of
controllers (the smallest type, pico-Blaze) for having
software control of the arithmetic and the area for
communications and decided that CBE is much faster for
the same funtionality.  FPGA is just too general for HPC.
It reminds me of the evolution of Thinking Machines in which
they started at the bit-level then built machines with Weitek
ALU's at the end of each row.
    I would like to add that the algorithms that I see are often
not purely SIMD though they are parallel.  CBE is partially
SIMD in that each processor can work on 4 4-byte words with
the same operation, but in addition there are 8 special
purpose processors each with their own instruction stream.
Examples of high speed-ups for SIMD problems is like picking
the low-lying fruit.  IMHO having many instruction streams
allows speed-up of algorithms that involve many logical
decisions -- what comes to mind is Monte Carlo simulation of
the flow of genes in pedigrees for finding the genetic
component of somatic attributes.  More generally, pointer
chasing.  MIMD at a high level of core (instruction sequencer)
integration would give a performance boost to an interesting
sector of algorithms of the pointer chasing type.
    I have not written algorithms for the CBE, so my remarks
on that aspect may be ignorant.
best regards,
Alan Scheinine
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