Beowulf: A theorical approach

James Cownie jcownie at
Fri Jun 23 01:38:13 PDT 2000

> Just as a matter of curiosity -- Once upon a time some two or three
> years ago I suggested on the list that a development company consider
> building a network communications device that plugged into the second
> CPU slot of a dual CPU board.

This is exactly how the Elan comms interface worked in the MEIKO CS-1,
(available circa 1992/3 ?). It plugged into the second M-Bus slot on a
dual SPARC CPU board.

It provided cache coherent remote user space access (including remote
DMA) with control from user processes in Solaris without requiring a
kernel trap. But _not_ an SMP model, although you had complete remote
store access, you had to _know_ that you wanted to access remote
store. Remote store was not memory mapped into the process address
space, so a simple load/store could never be remote. (I.e. it's a
message passing model, or what Cray called "shmem", but with full
cache coherence). There was also a little processor in there for
message sequencing and so on (which also ran in the user address
space, of course).

Been there, done that...

p.s. the current successor to this is the Quadrics' technology.

The reasons no-one does it any more are

1) You can't get the bus specs from the CPU vendors.
2) The CPU bus-specs change too fast for you to be able to keep up.

As a non-cpu vendor you're driven to working with something which has
a public specification and doesn't change every six months, which
currently means PCI.

-- Jim 

James Cownie	<jcownie at>
Etnus, Inc.     +44 117 9071438

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