[Beowulf] Acceptable rad limits for cluster rooms?

[Jim Lux]

At 10:54 AM 6/19/2006, Greg Lindahl wrote:
>On Mon, Jun 19, 2006 at 06:02:45AM -0700, Jim Lux wrote:
>
> > Bear in mind, though,
> > that the processor itself is probably pretty susceptible to SEU, and
> > doesn't have ECC internally.
>
>Processor *caches* do have ECC, and since they're more susceptible
>than the logic, this gets most of the benefit.

Some caches do, some don't.  And it's tough to find out exactly what they 
mean by ECC.  A bit of searching on Intel's website turned up this:
Integrated 2MB Level 2 Cache on Intel® Pentium® 4 Processor Extreme Edition 
3.73 GHz and 6xx
The 2-MB Advanced Transfer Cache (on-die, full-speed Level 2 cache) with 
8-way associative and Error Correcting Code (ECC) can improve overall 
performance by allowing the processor to have faster access to a larger 
amount of the most often used data.

But I haven't been able to find out any more details.



>  And some peripheral
>makers use ECC on all the rams in their chips, QLogic's FiberChannel
>HBAs are an example.


yes.. but, for instance, do they do writeback and/or scrubbing when a 
single bit error is detected, or do they just trust that by the time the 
error occurs again in the same word, that you'll have written new data?



>-- greg
>
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James Lux, P.E.
Spacecraft Radio Frequency Subsystems Group
Flight Communications Systems Section
Jet Propulsion Laboratory, Mail Stop 161-213
4800 Oak Grove Drive
Pasadena CA 91109
tel: (818)354-2075
fax: (818)393-6875
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