[Beowulf] "dual" Quad solution from Tyan
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Mark Hahn hahn at physics.mcmaster.caMon Feb 27 17:53:44 PST 2006
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> I'm responsible for the aquisition of my labs new cluster. I already had what's the purpose of the cluster? without a well-defined purpose, there's no way to evaluate the options... > here, in Portugal. The target machine I was looking for was 8 node with > dual processor Opteron (16 CPU). The machine that was at the presentation OK, so 8 dual-socket nodes will deliver an aggregate memory bandwidth of 16*6.4 GB/s, and a capacity of 64 dimms. > http://www.cybernex.co.uk/tyan_vx50_quad_opteron_servers.htm afaikt, this is a ladder design: c-c-c-c | | | | c-c-c-c which is 5 hops corner-to-corner, with a bisection of 3.2 GB/s per node. half the aggregate memory bandwidth and capacity. > which means 8 CPU, dual core. And all are connect with hypertransport > which meand I got ready of latency I figure. So... well, HT latency is better than gigabit, if that's what you mean. I've never read a good evaluation of MPI implementations on this kind of hardware. don't forget that dual-core is lower clocked. > The professor head of the lab wants me to know "if that is so good why > isn't everyone buying one?" who says it's so great? the HT fabric is pretty far from a "perfect" low-latency 16-port crossbar, for instance. also, is it really cheaper? how about if you compare to four 2-socket DC nodes?
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