gromacs benchmark and quad Xeons

[Velocet]

On Tue, Jun 18, 2002 at 04:28:04PM -0500, Richard Walsh's all...
> On Tue, Jun 18, 2002 at 02:14:02PM -0400, Velocet wrote:
> ...
> > Are the original rpms for gromacs which are generally compiled for P2/MMX
> > going to be absolutely the worst possible situation for a Xeon? Or should
> > they work relatively near best-speed (minus missing SSE and SSE2 instructions,
> > though I dont even know if GCC gives the full set of either for a hand
> > compile). 
> > 
> > What's wrong here? Any ideas?
> 
> My first reaction is to wonder what your memory foot print is ...
> the bandwidth of all quad's I have seen (except the ES-45 with 
> Compaq's typhoon chipset and cross-bar) has been lousy. If you
> are not running mostly/completely in cache this could be an
> issue.  Competition from all four CPUs for bandwidth could kill
> performance. 

but with DDR ram on a dual Tyan 2460/66 board I saw like 2.4x or some odd
speedup with 2 cpus over 1. (superlinear speedup) - as I mentioned,
possibly due to reduced cache thrashing.

> Have your tried running on one CPU? Can you shrink the test
> case to make sure it is cache and then look at the performance?
> How does stream performanc on this quad?

Whats a good test?

I'll try out one CPU and see what happens. Too bad the thing is
slated for production later this week - wont be able to put nasty
calculation stuff on it anymore... :(

Not many quad xeons lying around just waiting for a thrashing :)

Anyone got one handy? :)

I'd love to see some 8-way stuff too. Takers?

/kc

> 
> 
> rbw
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-- 
Ken Chase, math at velocet.ca  *  Velocet Communications Inc.  *  Toronto, CANADA