low cost high speed interface was: custom cluster cabinets (was Re: 1U P4 Systems)

[Jim Lux]

<big snip>
>>
>With the dropping costs of CPUs and chipsets what we are now seeing is
>that the cost of the Myrinet and SCI parts are several times the cost of
>the CPU and chipset. Maybe someone will make a low cost low latency high
>bandwith ASIC soon to fit the growing market.
>

You might take a look at SpaceWire (aka IEEE 1355.2). Very low cost, high
speed (150 Mbps today, 400 in next year) low latency serial communications
with nonblocking wormhole routers (i.e. the router just looks at the header
to figure out where to send it and doesn't buffer up the whole packet).  The
hardware deals with bandwidth sharing among multiple links in parallel, etc.

Today, it's being pushed for space applications (hence the name), but
University of Dundee has just finished a VHDL core for the interface and
router, and is starting to test, and expects to be done in a year.  Today,
you can buy Intellectual property from a company called 4links (in England)
to fit in the smallest Xilinx FPGA to implement it. The full up core and
router are targeted to the Virtex parts, which are quite large, and
expensive.

Whether someone will market an inexpensive ASIC to support it is an open
question.  There are some large consumer electronics firms looking at it
(since it can easily handle video rates, and is much cheaper and simpler
than 1394 (FireWire)).

Spacewire PCI cards are wretchedly expensive today ($10K for a three link
card) but that's because they are using a $5K part designed for space
applications, which are low volume and not price sensitive to the degree
that consumer, mass market, is.  If one were interested in implementing the
interface on the mobo with a motherboard chipset, the cost would be quite
low for the additional hardware needed.

Full Disclosure: I am on the IEEE 1355.2 committee and have been using the
interface in a lab application for a year now, so I am a bit biased.